Browse Prior Art Database

Low Leakage Implanted Source

IP.com Disclosure Number: IPCOM000083667D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Geipel, HJ: AUTHOR [+2]

Abstract

A process technique yielding excellent (junction leakage densities < 1fA/mil/2/) N/+/ P ion implanted source-drain junctions, that is compatible with standard metal-oxide semiconductor field-effect transistor (MOSFET) fabrication processing, is described. The key points are the initial wafer clean, implementation of an ion implant process using no photoresist as an implant mask, and post implantation cleaning.

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Low Leakage Implanted Source

A process technique yielding excellent (junction leakage densities < 1fA/mil/2/) N/+/ P ion implanted source-drain junctions, that is compatible with standard metal-oxide semiconductor field-effect transistor (MOSFET) fabrication processing, is described. The key points are the initial wafer clean, implementation of an ion implant process using no photoresist as an implant mask, and post implantation cleaning.

In Fig. 1 the wafer is initially cleaned by a multicycle HF; HNO(3)/ HF-Huang sequence. The initial thick oxide thickness 2 is increased from its nominal value approximately four times Rp, where Rp is the projected ion range. An optional screen oxide 4 of a few hundred angstroms may be deposited after SD open. The wafer 1 is ion implanted at a suitable energy and dose.

Directly after implantation, the wafer is plasma ashed in O(2) for removal of residual hydrocarbons. The additional thick oxide thickness 3 is removed as depicted in Fig. 2. During this step the screen oxide 4 would be removed also. A Huang clean without HF is employed, followed by a drive-in and an anneal at higher or equal to 1000 degrees C.

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