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Browse Prior Art Database

FET Capacitance Reduction Method

IP.com Disclosure Number: IPCOM000083673D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Greenhaus, HL: AUTHOR

Abstract

This description is directed to the manufacture of field-effect transistor (FET) semiconductor devices using a doped oxide layer appropriately etched to form source and drain region locations and followed by a drive-in and oxidation step.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

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FET Capacitance Reduction Method

This description is directed to the manufacture of field-effect transistor (FET) semiconductor devices using a doped oxide layer appropriately etched to form source and drain region locations and followed by a drive-in and oxidation step.

The improvement comprises prior to drive-in, depositing or otherwise forming a layer or film of silicon nitride over the doped oxide regions and the etched out substrate areas as an antioutdoping cap and implant mask, followed by the conventional drive-in and subsequent surface tailoring step by implantation through the silicon nitride.

This procedure avoids undesirable capacitance formation where doped oxide is protected with photoresist, in order to prevent its removal from one or more diffused areas which inherently protects a portion of oxide formed during conventional drive-in and oxidation, which causes undesirable capacitance caused by the subsequent oxide removed.

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