Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Cascode Shift Register

IP.com Disclosure Number: IPCOM000083674D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

Described is a cascode shift register in which the cascoding results in a lower power dissipation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Cascode Shift Register

Described is a cascode shift register in which the cascoding results in a lower power dissipation.

The circuit shown in the figure comprises two stages A and B of an N-stage shift register. The biasing scheme provides a path from +V to ground from any stage of the first shift register A, through any stage of the shift register B for a common bias current I. Hence for any performance the power is cut in half. Half the stages would be at the high-voltage level and the other half at the low-voltage level.

A translation circuit is required at least once between a high-level stage and a low-level stage, but no translation is required or needed going from low to high. The lower stages are somewhat disturbed by the voltage excursion at the shift A nodes, but the lower bit is differential and provides sufficient rejection. The concept as shown herein can be extended to N levels, if enough supply voltage +V is available.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]