Browse Prior Art Database

Wafer Packaging With an Interposer

IP.com Disclosure Number: IPCOM000083678D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Joshi, KC: AUTHOR

Abstract

With growing emphasis on large-scale integration (LSI), a key problem facing circuit package designers is in providing power in close proximity to the circuits. For example, in a package including a 3'' to 4'' diameter chip carrier 10, the power drop on lines between the center and outer edge is substantial, such that the actuation of the circuits on the chip carrier becomes difficult to impossible. Therefore, power must be provided to each chip 11 on the chip carrier 10, or to an island consisting of a group of chips or a group of diffused circuits.

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Wafer Packaging With an Interposer

With growing emphasis on large-scale integration (LSI), a key problem facing circuit package designers is in providing power in close proximity to the circuits. For example, in a package including a 3'' to 4'' diameter chip carrier 10, the power drop on lines between the center and outer edge is substantial, such that the actuation of the circuits on the chip carrier becomes difficult to impossible. Therefore, power must be provided to each chip 11 on the chip carrier 10, or to an island consisting of a group of chips or a group of diffused circuits.

A simple method to achieve power distribution is through an interposer 12 that is stacked on a main substrate 13. The package further includes power terminals 14 interconnected between the chip carrier 10 and the interposer substrate 12. The stacking is accomplished by use of pins 15 joined to the interposer substrate 12 and the bucket/pads in the substrate 13.

The package may incorporate a coolant jacket 16 to facilitate the cooling of the circuitry. Appropriate sealing 17 can be incorporated depending on needs.

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