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Thermally Enhanced Multilayer Ceramic Substrate Structure

IP.com Disclosure Number: IPCOM000083679D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kerjilian, QK: AUTHOR [+2]

Abstract

This is a thermally enhanced multilayer ceramic structure particularly adapted for LSI applications and having high module power dissipation capability.

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Thermally Enhanced Multilayer Ceramic Substrate Structure

This is a thermally enhanced multilayer ceramic structure particularly adapted for LSI applications and having high module power dissipation capability.

The multilayer ceramic chip carrier 10 approach provides a plurality of internal power and signal planes 11 within the substrate 12, designed to accommodate high-density LSI (large-scale integration) chips 13, and which leaves the chip side surface of the substrate 12 free of any circuit wiring and available for heat sink mounting. The structuring is accomplished by using a ceramic heat sink 14, which is an integral part of the multilayer ceramic package.

A ceramic heat sink package will have a higher fin efficiency, because its thermal conductivity is 50 to 60% higher than that of KOVAR*. In addition, by making the heat sink 14 an integral part of the multi-layer ceramic substrate 12 one interface and the thermal path of substrate-to-heat sink is eliminated, resulting in a lower overall module thermal resistance.

To further reduce the heat flow path resistance, a metallic alloy heat spreader plane 15 is added between the first and second ceramic layers such that it clears all power and signal lines from the chip to the lower planes, to thereby avoid short circuiting. The function of this plane is to spread the heat from the chip sites to the base of the heat sink 14. On multichip modules, the heat spreader plane 15 has an added function in that it provides a more balanced thermal distribution, when the chips are powered at different power levels.

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