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Dielectric Isolation Using a High Resputtering Deposition

IP.com Disclosure Number: IPCOM000083696D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Lechaton, JS: AUTHOR [+2]

Abstract

The present process for dielectric isolation is by the thermal oxidation of Si through a Si(3)N(4) mask, which creates a nonplanar structure because of oxidation under the edge of the Si(3)N(4) and trenching at the post etching process steps.

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Dielectric Isolation Using a High Resputtering Deposition

The present process for dielectric isolation is by the thermal oxidation of Si through a Si(3)N(4) mask, which creates a nonplanar structure because of oxidation under the edge of the Si(3)N(4) and trenching at the post etching process steps.

Described is a method for obtaining a planarized sputter deposited dielectric isolation, by using the natural contour characteristic of sputter deposition. The dielectric isolation window is opened in the masking layer by conventional methods and recessed back, so as not to leave a ledge over the isolation trench.

The dielectric material is sputter deposited at a high-resputtering rate resulting in a thin region at the edge of the silicon step. The thin portion is etched through in a blanket etch exposing the edge of the mask material. The mask material is then etched away, lifting off the dielectric over the device area.

Since the dielectric is sputter deposited, no bird's beak is formed. The dielectric isolation is self-aligned and a planarized structure is obtained. It is believed that the use of Si(3)N(4) on silicon causes crystallographic dislocations in the silicon. This method does not require Si(3)N(4) in direct contact with the silicon.

If the sputtered dielectric is SiO(2), then a short (~30 min) high-temperature (~1000 degrees C) oxidation cycle will densify the sputter SiO(2) and also grow a thin thermal oxide film at the SiO(2)-silicon interface. This wil...