Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

FET Line Recovery Circuit With Normalized Delay Feature

IP.com Disclosure Number: IPCOM000083700D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Hannaford, CW: AUTHOR [+2]

Abstract

The line recovery circuit depicted in the drawing contains a low impedance charging switch, which is turned on when the line voltage reaches a certain threshold above the downlevel voltage. Provision is made for causing the switching threshold to vary directly with changes in downlevel voltage, whereby the line is recharged independent of variations in downlevel line voltage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 94% of the total text.

Page 1 of 2

FET Line Recovery Circuit With Normalized Delay Feature

The line recovery circuit depicted in the drawing contains a low impedance charging switch, which is turned on when the line voltage reaches a certain threshold above the downlevel voltage. Provision is made for causing the switching threshold to vary directly with changes in downlevel voltage, whereby the line is recharged independent of variations in downlevel line voltage.

This circuit establishes a switching threshold with respect to the line voltage, not ground, and hence normalizes delay variations due to variations in the downlevel voltage. When driver device TN turns off, the line (CL) is initially charged by current source I1 (T1) and reference current Iref (T4) through devices T2 and T5, respectively.

When the line voltage charges to within a threshold of the reference (node Vref), device T2 turns off allowing the current I1 to charge the gate of device T3, turning it on and rapidly charging the line. At the same time the reference voltage Vref charges positively, but at a slower rate, holding device T2 off.

When driver device TN turns on again for discharging the line CL, device T2 turns on extremely fast due to the higher reference voltage, since node Vref tracks the line voltage. This results in turning off device T3, allowing a quick discharge of the line CL through TN. Here again, the reference voltage tracks the line voltage at slower rate, making device T2 heavily conductive and holding off...