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Reference Voltage Circuit Layout From a TTL Cell

IP.com Disclosure Number: IPCOM000083710D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Colao, E: AUTHOR [+3]

Abstract

A layout technique to implement a current switch reference voltage circuit, from a transistor-transistor logic (TTL) cell layout, is depicted in the drawing.

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Reference Voltage Circuit Layout From a TTL Cell

A layout technique to implement a current switch reference voltage circuit, from a transistor-transistor logic (TTL) cell layout, is depicted in the drawing.

The structure of the input device of the TTL cell forms both a Schottky barrier diode (SBD) and a PN junction diode, resulting in an increased functionality of the chip, since only one, instead of two, isolated active devices are needed to construct the circuit.

The layout of Fig. 1 shows the connections of the TTL circuit to form the current switch reference voltage circuit of Fig. 2.

The collector voltage VCC is connected to one contact of resistor R1, while the other contact is connected by metal to the Schottky contact S. An SBD is formed under contact S to the epi layer, to which the subcollector is common. Contact C makes contact to this subcollector. Another metallization connection is made between contact C and the base contact B. Contact E is the emitter- diffusion contact and is connected to another resistor R2 elsewhere on the chip.

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