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Browse Prior Art Database

High Speed Switching Matrix

IP.com Disclosure Number: IPCOM000083719D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Nestork, WJ: AUTHOR

Abstract

This switching matrix provides a high-speed switching matrix between any two lines, as for example basic storage module to central processing unit or central processing unit to file.

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High Speed Switching Matrix

This switching matrix provides a high-speed switching matrix between any two lines, as for example basic storage module to central processing unit or central processing unit to file.

The matrix shown in Fig. 2 is operatively connected to the decoder illustrated in Fig. 1. A binary code, inputted to lines X and Y (Fig. 1), are logically decoded into control lines A', A', B', B', C' and C'. The output lines of Fig. 1 are operatively connected to the corresponding inputs in Fig, 2,

In operation, if a binary code indicates that A wishes to communicate with B, the lines A' and B' are at ground and A' and B' are at an uplevel. This uplevel is designated to be more positive than the line uplevels. This turns off transistors 2, 4, 6, 8, 10 and 12. Since C' is up, transistors 5, 11, 17, 18, 16 and 14 remain on.

For purposes of illustration, assume that A has a positive signal to transmit to B whose line is normally at a downlevel. This turns off transistors 3 and 1 with transistors 2 and 4 already off, which places an uplevel into diodes 1 and 5. With the clock at an uplevel, however, this signal is blocked since transistors 19 and 20 are on.

When the clock drops to ground, the uplevel of diode 5 will appear on the B data line and be transmitted to box B. This also turns off transistors 9 and 7 and places uplevels on diodes 2 and 4, thus latching up the circuits until the clock again goes to an uplevel which resets the system for next data tran...