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Chip in Place Test Data Verification

IP.com Disclosure Number: IPCOM000083728D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Lange, LK: AUTHOR

Abstract

Presently for each chip part number mounted on a module, it is necessary to supply a test data file containing a set of input stimuli and output responses to properly "test" the given part.

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Chip in Place Test Data Verification

Presently for each chip part number mounted on a module, it is necessary to supply a test data file containing a set of input stimuli and output responses to properly "test" the given part.

In a great majority of cases, the test data file for the wafer test may be used for the module test. In other cases, in a given module location some inputs, outputs or input-to-output combinations are connected For this case, a new test data file is required, since the wafer test assumed all inputs/output switching independence.

If for some reason the test data is incorrect, the possibility exists of removing good chips, or damaging the module substrate through chip removal and chip joining.

The solution is to verify the test data before module test by simulating the module, thus finding the need for adding personality at chip test time. Personality can be added, either through commoning of the chip test probes or by putting a chip on a carrier and wiring together the proper input/output pad combinations. Such a procedure verifies the test data prior to module test.

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