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Digital Automatic Gain Control Circuit

IP.com Disclosure Number: IPCOM000083730D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Besseyre, J: AUTHOR

Abstract

Shown is a digital automatic gain control circuit (AGC) provided at the receiver end of a digital signal processor (demodulator of a modem, ultrafrequency receiver) for controlling the dynamics of the received signal, and consequently reducing the number of bits to be processed by the receiver processor.

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Digital Automatic Gain Control Circuit

Shown is a digital automatic gain control circuit (AGC) provided at the receiver end of a digital signal processor (demodulator of a modem, ultrafrequency receiver) for controlling the dynamics of the received signal, and consequently reducing the number of bits to be processed by the receiver processor.

This AGC circuit takes advantage of the characteristics of the companding law of the PCM samples. For transmission purposes, 12-bit linear PCM samples may be transformed into 8-bit companded PCM samples S comprising a sign bit s, three exponent bits TUV and four linear bits WXYZ. Bits TUV define 1 out of 8 amplitude segments and give the characteristics of the sample. Bits WXYZ define 1 out of 16 positions on a segment and give the mantissa of the sample. Input samples may be expressed by the following floating representation: SI(n) = s 2/TUV/. WXYZ

These input samples, the levels of which have to be controlled before being expanded and set to the processor, are applied on input 1 of the AGC circuit and bits TUV WXYZ are stored in register 2.

Gain control of companded samples SI(n) to the processor is performed by circuit 4, register 5 and expander 6, which provides 12-bit linear output samples SO(n) on output 7.

The AGC function is performed by a feedback control path comprising a squaring circuit 8, an accumulator 9, a leakage circuit 10 and a compander 11 for calculating a gain control factor k proportional to the energy in the signal. This factor is expressed by seven companded bits T(1)U(1)V(1) W(1)X(1)Y(1)Z(1) which are stored in register 12.

Input samples SI(n) are expanded in circuit 6 with an exponent v...