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Lateral Transistors as Active Guard Ring in FET Circuits

IP.com Disclosure Number: IPCOM000083731D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+3]

Abstract

The ever increasing use of bootstrap circuits (capacitive feedback) in integrated circuits leads to a frequently recurring problem, for example, in N-channel technology: An N/+/doped region is discharged to approximately 0 V. An adjacent line is switched from the positive supply voltage to 0 V. The bootstrap capacity transfers this negative voltage transition to the N/+/doped region causing it to adopt a strongly negative potential. If this potential drops below the substrate bias, the N/+/ region injects electrons into the P substrate, i.e., the p/N/+/ diode is forward biased. This affects the circuit behavior as follows: a) The minority carriers injected into the substrate may be collected in adjacent N/+/ doped regions, which causes spurious currents.

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Lateral Transistors as Active Guard Ring in FET Circuits

The ever increasing use of bootstrap circuits (capacitive feedback) in integrated circuits leads to a frequently recurring problem, for example, in N- channel technology: An N/+/doped region is discharged to approximately 0 V. An adjacent line is switched from the positive supply voltage to 0 V. The bootstrap capacity transfers this negative voltage transition to the N/+/doped region causing it to adopt a strongly negative potential. If this potential drops below the substrate bias, the N/+/ region injects electrons into the P substrate, i.e., the p/N/+/ diode is forward biased. This affects the circuit behavior as follows: a) The minority carriers injected into the substrate may be collected in adjacent N/+/ doped regions, which causes spurious currents. b) A considerable part of the injected current flow via the substrate to the respective power supply. The substrate series resistance may amount to several k omega. The injected current causes a voltage drop across the substrate series resistor, which leads to local changed in the device properties, for example, an increased threshold voltage of the field-effect transistors (FET's). c) When the N/+/ doped region which has been driven to a negative potential is recharged, a time loss occurs.

To eliminate these difficulties, it is proposed that the jeopardized doped region be surrounded by a protective doped region of the same conductivity type, so that in N-channel technology a lateral NPN and in P-channel technology a lateral PNP transistor is formed, across which the spurious injection current is extracted.

The illustration shows a schematic cross section of a lateral NPN transistor in N-channel technology thus formed. N/+/ region 1 to be protected (because it is liable to inject) may be, for example, the source or drain of a FET, as shown in the left part. Region 1 forms the emitter, substrate 2 the base, and protective diffusion 3 the collector of the protective bipolar (BIP) transistor structure...