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Stable Output Circuit for a Dynamic Shift Register

IP.com Disclosure Number: IPCOM000083744D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR

Abstract

A DC output stage to a dynamic shift register provides a static output which can recover from AC noise due to the clock. The output timing allows the circuit to drive other shift registers with the same timing. The output circuit saves chip area by eliminating the requirement of an inverter after the shift register output.

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Stable Output Circuit for a Dynamic Shift Register

A DC output stage to a dynamic shift register provides a static output which can recover from AC noise due to the clock. The output timing allows the circuit to drive other shift registers with the same timing. The output circuit saves chip area by eliminating the requirement of an inverter after the shift register output.

In the figure, the presence of Phi 1 charges the capacitor CO. On removal of phi 1, CO retains or discharges charge through T3 depending upon the output level transferred to the input through T6 or T1. An uplevel on T3 discharges CO, while a downlevel retains the charge provided by 0/1. T3 must have a width-to- length ratio to achieve a downlevel very quickly.

The presence of Phi 2 at T7 transfers the charge, if any, to C1. C1 is designed to avoid being temporarily charged to an uplevel when T7 turns on. C1 is also designed to prevent noise spikes from phi 2 being propagated to the output inverter comprising T4 and T5.

Increasing the time interval between phi 1 and phi 2 contributes to a reduced noise problem at the output. The signal stored on C1 appears in inverted form at output node B. T4 can be an enhancement or depletion device. T4 may also be arranged for linear load operation instead of the saturated operation, as shown in the figure.

The static inverter buffers the output to AC noise generated by the clocks phi 1 and phi 2. Additionally, the output signal does not require inversion as...