Browse Prior Art Database

Enhance Deplete Push Pull Driver

IP.com Disclosure Number: IPCOM000083746D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+3]

Abstract

An enhance/deplete push-pull driver is described having a bootstrapped output.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Enhance Deplete Push Pull Driver

An enhance/deplete push-pull driver is described having a bootstrapped output.

The figure shows a two stage push-pull inverter driver using depletion mode load devices. Field-effect transistor (FET) device A is a depletion mode load device, having its gate connected to its source and its drain connected to a drain voltage supply. The gate and source of FET A are connected to the drain of FET B whose gate serves as the logical input for the circuit. The source of FET B is connected to ground.

The devices A and B operate as a conventional depletion mode load inverter, with the output node being the source of FET device A.

This first output node is connected to the gate of a depletion mode device C. The source of depletion mode load FET device C is connected to the drain of enhancement mode logic device D, whose gate is connected to the gate of device B. The source of device D is connected to ground.

Operation of a conventional push-pull enhance/deplete inverter driver occurs, with the impedance of devices C and D being alternately high and low with respect to the output node. The operation of the circuit is improved by the inclusion of a bootstrap capacitor C(bs) between the gate and the drain of the depletion mode load device C.

In the operation of a circuit, when the decode data voltage is zero and MS voltage is zero, C(bs) is charged by the load device A. No current flows to the array through the output node until the signal volt...