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Push Pull Circuit

IP.com Disclosure Number: IPCOM000083747D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

Described is an improvement to a push-pull circuit, employing enhancement type and depletion type field-effect transistor devices.

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Push Pull Circuit

Described is an improvement to a push-pull circuit, employing enhancement type and depletion type field-effect transistor devices.

Described is a circuit for delaying a charging signal in a bootstrap capacitor, field-effect transistor (FET) circuit. The figure shows the circuit wherein a first inverter is comprised of a depletion mode FET load device QA and the enhancement mode FET device QB having a gate connected to the input signal.

The output node A of the first invertor is connected to the drain of the depletion mode device QE, whose source is connected to one electrode of the bootstrap capacitor CSTRAP at node C. The input connected to the gate of QB is also connected to the drain of the depletion load device Q delay, whose source is connected to one electrode of the capacitor CDELAY at node B. The other electrode of the capacitor CDELAY is connected to ground, as are the sources of the transistors QB and QC.

A second invertor having a bootstrap operation is comprised of the enhancement mode field-effect transistors QF and QG. QF is connected by the bootstrap technique with the capacitor CSTRAP connected between the gate QF and the source of QF. A drain of QG is connected to the source of QF and the source of QG is connected to ground.

Node C is also connected to the gate of the depletion mode FET device QH, whose drain is connected to the drain supply and whose source is connected to the output node D. The output node D is characterized b...