Browse Prior Art Database

Digital Addressing of Display Stations Via High Speed Shared Data Link Carrying Video Data

IP.com Disclosure Number: IPCOM000083769D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Bender, RR: AUTHOR [+4]

Abstract

Multiple display (head) stations which ordinarily have separate addressing connections to a common control unit (for supervisory and display video data communications), can be adapted to share a single high-speed (coax) cable CC as a common addressing and data link. The address information and other data can be sent in the same form; at baseband or modulated on a carrier frequency.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 2

Digital Addressing of Display Stations Via High Speed Shared Data Link Carrying Video Data

Multiple display (head) stations which ordinarily have separate addressing connections to a common control unit (for supervisory and display video data communications), can be adapted to share a single high-speed (coax) cable CC as a common addressing and data link. The address information and other data can be sent in the same form; at baseband or modulated on a carrier frequency.

A signaling protocol is required for distinguishing address intelligence from other data. This can be very simple. The control unit need only preface the header portion of each discrete communication "block" directed to a terminal with a series of "0" bit signals, understood by the station sets to represent a reset or alerting function.

An address generating repeater AGR between the control unit and cable acts as an adaptor to convert parallel address information, supplied to it by the control, into corresponding serial digital signals in the cable format. It inserts these signals immediately behind the first (or a selected) 0 bit of the "alert" series on the cable.

Address decoding adaptor logic circuits AD at the drop nodes of the individual display stations are "prepared" by the initial 0 bit of the alert train, to "relay" 0's to their respective display heads DH while receiving and holding the address bits. As the last address bit is received the address is decoded exclusively, enabling the a...