Browse Prior Art Database

Compatible Expanded Main Storage Addressability

IP.com Disclosure Number: IPCOM000083774D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Masog, CR: AUTHOR [+3]

Abstract

Apparatus including separate address translation and storage protection tables is provided for addressing main storage, which has been expanded to sizes extending beyond the addressing capacity of an address translation table, including both address bits and storage protection bits, and still enabling the use of programs written f-r the integrated table.

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Compatible Expanded Main Storage Addressability

Apparatus including separate address translation and storage protection tables is provided for addressing main storage, which has been expanded to sizes extending beyond the addressing capacity of an address translation table, including both address bits and storage protection bits, and still enabling the use of programs written f-r the integrated table.

The five high-order bits of the storage address in storage address register (SAR) 10, Fig. 1, simultaneously address one of thirty-two storage protection registers 20 and address translation registers 30. The storage protection registers contain protection keys for the referenced storage location. The address translation registers contain eight bits, seven of which are concatenated with the eleven lower order bits from SAR 10 to form an 18-bit address in main storage address register (MSAR) 40. The address in register 40 addresses main storage, not shown.

Registers 20 and 30 are loaded under program control by LOAD SPT and LOAD ATT instructions, respectively. The Q byte of these instructions (see IBM 5415 Processing Unit Theory - Maintenance - Diagrams SY31-0367-2 for instruction format) specifies the table and the register within the table to be loaded. The operand of the instructions is the data loaded into the selected register.

Heretofore, a table of registers, not shown, were structured whereby the registers contained both storage protection and address transla...