Browse Prior Art Database

Logic Array

IP.com Disclosure Number: IPCOM000083798D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Gardner, PL: AUTHOR

Abstract

This description concerns an array logic system formed as a single-chip component. The component is a rectangular metallization matrix with active inverting elements at each node, the metallization being interrupted at selected points to impose a desired logic function on the chip.

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Logic Array

This description concerns an array logic system formed as a single-chip component. The component is a rectangular metallization matrix with active inverting elements at each node, the metallization being interrupted at selected points to impose a desired logic function on the chip.

Fig. 1 is a schematic representation of a single node and its neighbors. It comprises a vertical north-south line V, a horizontal east-west line H, a north-east line NE and a south-west line SW joining lines V and H, an inverter with line NE as input and a line SW as output, and cutting points 1 to 6 on the lines.

At each node, it is possible to allow a signal to propagate further or stop, to change direction from V to H or vice versa, or to change polarity, by appropriately interrupting the lines at the cutting points. The following basic functions are possible: Function Leave Uninterrupted V to H true 3 and 4 H to V true or 1 and 2 V to H inverse 1 and 3 H to V inverse 2 and 4 V to V true 5 H to H true 6 V to V inverse 1 and 4(must interrupt5) H to H inverse 2 and 3(must interrupt6).

The functions can be combined at each node. Where lines are dotted, signals can be OR'ed or AND'ed depending on technology. For example, assuming that the DOT function is OR, the interrupting of 3 and 5 only will OR together the signal on north, west and east and drive the inverse onto south. The interrupting of 1, 4 and 6 commons north and south, while independently the inverse of east is driven onto west.

Desired logic functions of any complexity, subject only to the limits imposed by array dimensions, can be realized by routing input signals through the matrix and by inverting and/or dot ORing (or ANDing) at selected nodes. The routing and selection are achieved by providing appropriate interruptions in the metallization matrix, the interruptions being formed by superimposing the pattern of the interruptions over a mask used in forming the matrix.

The arrangement described above can be extended by replacing each single vertical and horizontal line by a group of such lines - see Fig. 2. In this case a logic block B consisting of N x N "cells" is used instead of a simple inverter, N being the number of lines in a group.

The input to each row of cells in block B is ta...