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Dynamic Gating Circuit

IP.com Disclosure Number: IPCOM000083836D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 28K

Publishing Venue

IBM

Related People

DeSimone, RR: AUTHOR

Abstract

This field-effect transistor (FET) gating circuit provides an output when two input signals are coincident and does not reset until one of the inputs is removed.

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Dynamic Gating Circuit

This field-effect transistor (FET) gating circuit provides an output when two input signals are coincident and does not reset until one of the inputs is removed.

The design of a FET circuit to generate an output at the coincidence of two input signals is simple enough, when the timing of the inputs is such that one of the inputs may always be used as a gate precharge pulse. However, when the input pulses are only partially coincidental such that either may occur first, or when input skews may be present, a more difficult problem is presented. Mismatch or skew in the fall times of the inputs further complicates the problem. This circuit overcomes these problems.

In describing the circuit, it is assumed coincidence detection between CP2 and CP3 is desired and that CP1 is available for use as a precharge signal. That is, CP1 is known to rise unconditionally prior to either of CP2 or CP3 and to fall after CP2 and CP3.

In the quiescent state, CP1, CP2 and CP3 are down, and CP1 is up causing nodes A, B, C and Vout to be at ground potential. When CP1 rises, capacitor C1 charges to within one threshold drop below the level of CP1, assuming CP1 equals V. CP1 drops and nodes A, C and Vout remain at ground. The three possible input conditions for CP2 and CP3 are described below.

1. Case I - CP2 rises before CP3. As node A rises toward CP2 potential through T2, node B is bootstrapped by C1 to allow node A to rise to CP2 potential. Simultaneously, node C rises to one threshold potential below node A and will remain charged until CP1 rises, because of the diode connection of T3 and the off state of T6. When CP3 rises, Vout will rise to within one threshold of CP3 potential through T4 and T5. Note that the charge trapped on node C keeps T5 conductive, even though CP2 may fall prior to the fall...