Browse Prior Art Database

Integrated MAOS Nonvolatile Memory Chips

IP.com Disclosure Number: IPCOM000083837D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Meulemans, DR: AUTHOR [+2]

Abstract

This technique prevents charge influenced breakdown in fully integrated nonvolatile memory chips, utilizing metal/aluminum oxide/silicon oxide/ semiconductor (MAOS) devices for both support and memory array devices.

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Integrated MAOS Nonvolatile Memory Chips

This technique prevents charge influenced breakdown in fully integrated nonvolatile memory chips, utilizing metal/aluminum oxide/silicon oxide/ semiconductor (MAOS) devices for both support and memory array devices.

Integrated MAOS devices require certain diffusions to withstand relatively high voltages used in writing nonvolatile memory elements. However, the use of aluminum oxide, which has a relatively large negative charge, may cause PN junctions which would normally have planar breakdown voltages of about 60 volts to have a charge influenced breakdown of from 15 to 30 volts, depending on the tunnel oxide thickness and the specific negative charge density. These diffusions include those source/drain diffusions associated with writing and erasing, in the support area of the chip, and the isolation diffusions separating the support area from the array area.

The figure shows a cross section of a typical chip illustrating a technique useful to prevent charge influenced breakdown in fully integrated MAOS technology. Epitaxially grown P-type semiconductor regions 10 and 12 are electrically isolated from each other, to form support and array areas by isolation diffusion 14 formed on semiconductor substrate 16.

In order to prevent charge influenced breakdown of the isolation diffusions, the thick thermal oxide 18 produced during reoxidization is left intact over the isolation diffusion, including any out diffusion. Any negativ...