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ID/VG Characterization Circuit

IP.com Disclosure Number: IPCOM000083841D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

This field-effect transistor (FET) test circuit provides for the characterization of drain-source current (IDS) versus gate voltage (VG) in the picoamp current range. The circuit is programmable, fast, accurate and suitable for in-line measuring of ID/VG characteristics.

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ID/VG Characterization Circuit

This field-effect transistor (FET) test circuit provides for the characterization of drain-source current (IDS) versus gate voltage (VG) in the picoamp current range. The circuit is programmable, fast, accurate and suitable for in-line measuring of ID/VG characteristics.

The figure shows a schematic of the circuit. An FET 10 to be tested is placed in a test socket, or probed, such that a known drain voltage VD is applied. A reference potential Vsub is applied to the substrate of FET 10.

A first high-input impedance differential amplifier 12 references the source electrode of FET 10 to ground and provides a current-to-voltage conversion such that the output of amplifier 12, Vo, equals IDS times R1. A second high- impedance differential amplifier 14 provides output voltage VG which is applied to the gate of FET 10.

At equilibrium, the inputs to amplifier 14 are equal allowing an externally supplied programmable input voltage Vin to accurately control IDS and to determine the gate voltage VG necessary to produce the desired IDS. The response of the circuit is not gain dependent.

Diode D1 protects the device under test from negative transients which may appear on the output of amplifier 14. The dual-feedback circuit in which amplifier 14 is connected provides high gain at equilibrium (Vo = Vin) and low gain under transient conditions.

The characterization circuit may be automated by providing a digital-to- analog converter for Vin. By s...