Browse Prior Art Database

Stable Short Channel MOSFET

IP.com Disclosure Number: IPCOM000083842D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR [+2]

Abstract

This metal-oxide semiconductor field-effect transistor (MOSFET) structure prevents variations of device characteristics, such as threshold drift, caused by carrier injection into the gate dielectric. The phenomenon is particularly troublesome in very short channel devices operated under input conditions, where gate drive (VGS-Vt) and drain-to-source voltage (VDS) are both large.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

Stable Short Channel MOSFET

This metal-oxide semiconductor field-effect transistor (MOSFET) structure prevents variations of device characteristics, such as threshold drift, caused by carrier injection into the gate dielectric. The phenomenon is particularly troublesome in very short channel devices operated under input conditions, where gate drive (VGS-Vt) and drain-to-source voltage (VDS) are both large.

Occurrence of the problem is most noticeable in driver devices where gain is dependent upon a large width-to-length ratio (W/L). The problem may be avoided by increasing channel length, causing input gate capacitance to increase, or by lowering gate drive or VDS, both of which reduce performance.

Fig. 1 is a schematic plan view of a device which enables the problem to be minimized, while maintaining desired high-power supply levels and without significantly reducing performance. A single FET is replaced by a dual-gate FET having a drain diffusion, usually connected to a power supply potential VD, and a source diffusion, connected to an output load to be driven. Intermediate the source and drain is an electrically floating source/drain, forming a source electrode for an upper FET and a drain electrode for a lower FET.

Fig. 2, is a circuit representation of the FET of Fig. 1 and shows the various voltage relationships between the two series connected transistors T1A and T1B. The transistors are designed so that VDS T1A and VGS-Vt T1A are below the allowed maximum...