Browse Prior Art Database

Two Device Storage Cell

IP.com Disclosure Number: IPCOM000083843D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Arzubi, LM: AUTHOR

Abstract

This field-effect transistor (FET) memory cell circuit provides improved performance over conventional single FET/capacitor memory cells, such as described in U. S. Patent No. 3,387,286 by Dennard.

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Two Device Storage Cell

This field-effect transistor (FET) memory cell circuit provides improved performance over conventional single FET/capacitor memory cells, such as described in U. S. Patent No. 3,387,286 by Dennard.

As shown in Fig. 1, the memory cell, intended for arrangement in an array of k word lines, WLk and j bit lines, BLj, Includes two metal-oxide semiconductor (MOS)FET devices T1 and T2 which are capable of coupling stored charge in storage capacitor Cjk to either of two separate bit lines, BLj1 or BLj2. T1 and T2 are responsive to decoded word lines WLk1 and WLk2, respectively.

By accessing the array through both pairs of bit/word lines in an alternate fashion, memory cycle time may equal access time. When one bit line is being recovered, storage capacitance Cjk may be accessed through the other bit/word line pair.

Another advantage of the memory cell is that provisions can be made for sequential accessing of a plurality of bits associated with a single word line, as might be implemented in a writable control store. In this case, since the next address to be requested is known, it can be sensed earlier through sense latches connected to bit lines not being used at the time. When the request for data arrives, only the proper bit line needs to be decoded. In this manner by alternating the sense latches, the access time will only be dependent upon the decoding time of the bit lines, thus making the array appear to have faster access time.

In addition...