Browse Prior Art Database

Dynamic One Device Storage Cell With Nonvolatile Backup Mode

IP.com Disclosure Number: IPCOM000083844D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Chang, JJ: AUTHOR [+3]

Abstract

This dynamic single field-effect transistor (FET)/capacitor memory cell avoids the problem of data loss, when a system power failure occurs in a volatile storage system. The system provides for quick transfer of dynamic data to a nonvolatile form which requires no external power to sustain.

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Dynamic One Device Storage Cell With Nonvolatile Backup Mode

This dynamic single field-effect transistor (FET)/capacitor memory cell avoids the problem of data loss, when a system power failure occurs in a volatile storage system. The system provides for quick transfer of dynamic data to a nonvolatile form which requires no external power to sustain.

After power is reestablished, data is retrieved from the nonvolatile storage and rewritten in dynamic form. A variable-threshold region used to nonvolatively store data is reset to a low-threshold condition, after the dynamic mode of operation is reestablished.

The figure shows a typical memory cell and includes a semiconductor substrate 10 into which is diffused a bit line BL, which is common to a plurality of memory cells. Overlying the surface of substrate 10 is a multiple thickness dual dielectric of silicon dioxide (SiO(2)) and silicon nitride (Si(3)N(4)). Adjacent to bit line BL and in field applying relation to the dual dielectric is an isolation electrode ISO, preferably formed of polycrystalline silicon. Spaced from ISO and formed at the same time is a storage node electrode STOR, also formed of polycrystalline silicon.

Between ISO and STOR is a third word line electrode WL, which is isolated from ISO and STOR by thermal oxide layer 12 grown on the polycrystalline lines. The dual dielectric under ISO and STOR is formed to provide a fixed-threshold response, while the dielectric under WL provides a variable-threshold response, having writable high and low-threshold conditions.

The memory cell operates as follows: VOLATILE MODE OPERATION.

Assume that the interface under WL is initially in the low-threshold state. 1. Write.

The device is written in a similar manner to a one-device cell. Electrodes ISO and WL provide a channel to the storage node under electrode STOR. The potential well under STOR is filled if the bit line diffusion BL is at 0 V '0' and remains empty if the diffusion is at 10 V '1'. Nonselected words have WL at 0 V. 2. Standby.

All WLs are at 0 V, thus isolating the charge. Note that this memory will need refreshing like other charge storage memories. 3. Read.

Reading may be accomplished in any manner compatible with the volatile one-device memory cell.

NONVOLATILE MODE...