Browse Prior Art Database

Multifunction Store Microinstruction

IP.com Disclosure Number: IPCOM000083864D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Callahan, RW: AUTHOR [+5]

Abstract

Efficiently managed data processing systems have independent subsystems for controlling central storage, central processing and source/sink (input/output) operations; each unit or subsystem having its own program and controls for program execution. In such systems, the interface between storage control unit(s) and source/sink unit(s) can be quite sophisticated.

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Multifunction Store Microinstruction

Efficiently managed data processing systems have independent subsystems for controlling central storage, central processing and source/sink (input/output) operations; each unit or subsystem having its own program and controls for program execution. In such systems, the interface between storage control unit(s) and source/sink unit(s) can be quite sophisticated.

This imposes demands on each Source/Sink Unit (SSU) for highly efficient management of its linkages to the storage control unit(s). Storage-bound traffic both synchronous and asynchronous must be suitably prioritized. The SSU's should be capable of balancing the storage-bound traffic load relative to plural storage control units. The S:SU should offer a variety of multiplexing services.

An SSU for this type of service is implemented by combinatorial use of hard- wired logic and microcode (both fixed and changeable). For execution of storage transfer operations in this type of environment, the following Store microinstruction is used. The interface environment in the following example consists of two SSU's and two storage control subsystems interfacing via two busing links (eight byte paths) which are used to pass: commands, modifiers, counts, addresses (both virtual and real), SSU identity, SSU status and variable- size blocks of data.

The Store microinstruction contains 32 bits as follows:

Bits 0-4: Microinstruction Type (Op Code).

Bits 5-7: Data Count field.

Bits 8-14: Local Store Address of Main Storage Address.

Bit 15: Segment/Displacement (S/D).

Bits 16-19: Command Field (CF).

Bit 20: Partial Write (PW).

Bit 21: Real/Nonreal.

Bit 22: Synchronous/Asynchronous (S/A).

Bit 23: Indirect/Direct (I/D).

Bit 24: Odd/Even (O/E).

Bit 25: Local Store/Local Buffer Register (LS/LB).

Bits 26-31: Internal Data Address (used with Bit 25).

Actions instituted by these fields are further defined with reference to the single figure as follows:

Bit 20 (Partial Write) locates data transfer count information to be passed to the storage subsystem controls. A "i" signifies that the count is modifiably contained in SSU local storage, in a space (mapped in the drawing) preceding the main store segment address identifier (H). If the bit is "0" the count is taken from the count field (Bits 5-7). This allows addressing integrity to be preserved when the beginning or end of a data record is off sixteen-byte address boundaries.

The data count (in byte units) varies from a value of one to a value of fifteen and is variable for every record currently being processed. Without the foregoing

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indirectly modifiable count function, a separate microinstruction would...