Browse Prior Art Database

N Sag Utilizing Porous S Technology

IP.com Disclosure Number: IPCOM000083879D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Peressini, P: AUTHOR [+4]

Abstract

A self-aligned gate (N-SAG) field-effect transistor (FET) structure can be obtained using a silicon (Si) gate, by incorporating porous Si technology into standard FET processing. The process is as follows:

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N Sag Utilizing Porous S Technology

A self-aligned gate (N-SAG) field-effect transistor (FET) structure can be obtained using a silicon (Si) gate, by incorporating porous Si technology into standard FET processing. The process is as follows:

1. Grow thick field oxide SiO(2) and remove in source, drain and gate regions, as shown in Fig. 1, by standard photolithography techniques.

2. Grow gate insulation and delineate gate region, as shown in Fig. 2, by standard photolithography techniques.

3. Grow polycrystalline Si on entire wafer and make porous, by anodically etching on a hydrofloric and electrolyte in regions directly contacting the Si substrate, as shown in Fig. 3. By utilizing a Si etch, the porous regions can be removed without significant removal of the remaining poly Si. This would eliminate the following Step 4.

4. Oxidize. Since the oxidation rate of porous Si is much greater than nonporous Si, the Fig. 4 structure can be achieved.

5. Remove by etching the SiO(2) and perform source and drain diffusion using the Si gate and Si-SiO(2) as self-aligning features, as shown in Fig. 5. Ion implant can alternatively be used, since etch bias of the mask is eliminated by the Si land over the field oxide.

6. Reoxidize. The floating Si electrode is an added feature, as shown in Fig.


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