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Preventing Surface Parasitic Currents in Lateral Bipolar Transistors

IP.com Disclosure Number: IPCOM000083885D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR [+4]

Abstract

The operation of lateral bipolar transistors may be affected by surface parasitic currents caused by metallic lines on the surface of the chip, where the insulation between the lines and the chip is quite thin.

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Preventing Surface Parasitic Currents in Lateral Bipolar Transistors

The operation of lateral bipolar transistors may be affected by surface parasitic currents caused by metallic lines on the surface of the chip, where the insulation between the lines and the chip is quite thin.

In the figure, a lateral bipolar PNP transistor comprising emitter and collector regions 2 and 4, respectively, and an N base region G is formed in a semiconductor substrate 8. Metallic contacts 10 and 11 are formed through windows in insulation layer 12 to the emitter and collector regions 2 and 4. The personalization pattern of the first level metallization allows the metallization to overlap base region 6.

Due to the small thickness of insulator 12, which may be in the order of a few thousand angstroms, the surface of the base region 6 may become inverted if as little as two volts is applied to conductor 10. The current thus collected by collector 4 is not only the bipolar current, but also the current from the field-effect transistor. The latter is proportional to the bias on collector metallization 10 and the equivalent thickness of insulator 12.

This undesirable current can be maintained at acceptable levels, by insuring either that the personalization pattern precludes the possibility that a conductive metal line is disposed over the base region 6 or by insuring the potential in the line is never high enough to cause inordinately high-parasitic currents.

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