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# Current Source Bias Generator

IP.com Disclosure Number: IPCOM000083893D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 39K

IBM

## Related People

Gittleman, D: AUTHOR [+2]

## Abstract

The drawing depicts a regulator circuit which provides an output OP equal to (1+f) (Vbe), where f = R1/(R1 R2). The output voltage OP serves as a reference for the current sources. The advantage of this circuit is that constant currents (IS1, IS2, - - ISN) are obtained substantially independent of power supply VN tolerance.

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Current Source Bias Generator

The drawing depicts a regulator circuit which provides an output OP equal to (1+f) (Vbe), where f = R1/(R1 R2). The output voltage OP serves as a reference for the current sources. The advantage of this circuit is that constant currents (IS1, IS2, - - ISN) are obtained substantially independent of power supply VN tolerance.

Operationally, the output voltage OP is: 1) V(OP) = VN+Vbe(T3)+Vbe(T2)+Vbe(T1) R1 over R1+R2 - Vbe(T5) 2) V(OP) = VN+IS1 x RL1+Vbe(TL1).

All Vbe's are the same, because the voltages across the devices are proportional to the logarithm of their current" Thus, even if the current densities in devices are different, the voltage across the devices Vbe will be nearly the same (within track limit).

From equations (1) and (2):

3) IS1 = Vbe R1 over R1+R2 / RL1.

From equation 3), it is clear that the constant current IS1 is fairly independent of device absolute tolerance and depends upon resistor track among R1, R2 and constant-current source resistors (RL1, --- RLN). Since the circuit may be used as part of an integrated chip, the resistor track is within a few percentile. Thus good constant-current sources (IS1, IS2, ISN) are provided.

The IBL current fluctuations at the emitter terminal of T5, due to load current (IS1, IS2 ---ISN) variations, are reduced by a factor of Beta. Therefore, the voltage variations of OP is minimal.

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