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Glitchless T/2/L Latch Utilizing Single Clock Input

IP.com Disclosure Number: IPCOM000083899D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR

Abstract

The circuit depicted is a T/2/L Latch which performs the logical function DC + CZi = Zf. The use of a single-phase clock input C, as opposed to the common C, C clock inputs, eliminates clock glitches caused by skew of the clock inputs.

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Glitchless T/2/L Latch Utilizing Single Clock Input

The circuit depicted is a T/2/L Latch which performs the logical function DC + CZi = Zf. The use of a single-phase clock input C, as opposed to the common C, C clock inputs, eliminates clock glitches caused by skew of the clock inputs.

The base pull-down circuit R6, R7 and DA of transistor TZ allows the proper ratio of R5 to R6 R7 to be maintained for the output uplevel Zf, while limiting the "on" drive to TZ, thus diminishing the extent of the ground bounce induced glitch.

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