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Glitchless Coincidence Latch

IP.com Disclosure Number: IPCOM000083900D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR

Abstract

Fig. 1 depicts a coincidence latch where a change of state thereof occurs only when the inputs have the same state and the state is different from the output state, i.e., A = B not= Zi.

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Glitchless Coincidence Latch

Fig. 1 depicts a coincidence latch where a change of state thereof occurs only when the inputs have the same state and the state is different from the output state, i.e., A = B not= Zi.

The circuit may be considered as two in-phase latches. Latch 1 where input A is considered data and input B is considered clock. Latch II where input B is considered data and input A is considered clock. The output is fed back to the clock input blocks 2 and 3. The combined latch is, in itself, glitchless.

Fig. 2 illustrates that if an in-phase block of delay is placed between A and B such that B = A + delay, glitches appearing at A will not be propagated provided that the pulse width of the glitch is less than the delay of that block.

This circuit has potential usage in phase-locked loop applications and in asynchronous machines.

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