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Post Oxidation Annealing of Field Effect Transistors to Reduce Fixed Charge Levels

IP.com Disclosure Number: IPCOM000083903D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Burkhardt, PJ: AUTHOR [+4]

Abstract

In fabricating field-effect transistor (FET) devices, charge reduction in the gate insulator is essential to obtain device stability. This charge reduction is conventionally reduced by a post oxidation anneal in a reducing or neutral atmosphere. Great care must be exercised to keep the level of contamination in the furnace to very low levels.

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Post Oxidation Annealing of Field Effect Transistors to Reduce Fixed Charge Levels

In fabricating field-effect transistor (FET) devices, charge reduction in the gate insulator is essential to obtain device stability. This charge reduction is conventionally reduced by a post oxidation anneal in a reducing or neutral atmosphere. Great care must be exercised to keep the level of contamination in the furnace to very low levels.

In this process, the post oxidation anneal procedure is performed using an RF heated susceptor to heat the wafers, while maintaining cold furnace tube walls. The cold walls apparently act as a gettering sink for the contaminant ions, particularly sodium ions.

As shown wafers 10 are supported on graphite susceptor 12 heated by induction coils 14, powered by an RF power source 16. The induction heating heats susceptor 12 without significantly heating up the walls of furnace 18.

The apparatus pictured is similar to the apparatus used in conventional chemical vapor deposition systems. The atmosphere may be argon, nitrogen or forming gas, introduced through inlet 20 and exhausted through outlet 22.

Using the process, mobile ion charge levels have been reduced from 10/12/ atoms cm/2/ to 10 atoms/cm/2/, while fixed charge levels have been reduced from 10/11/ to less than 10/10/ atoms/cm/2/.

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