Browse Prior Art Database

Device for Fast I/O Selection

IP.com Disclosure Number: IPCOM000083906D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Favre, P: AUTHOR

Abstract

This device is linked to an interruptible computer by a data bus 17, interrupt level lines 18 and input/output (I/O) tag lines 20. When it requests service, it selects itself among all the I/O units connected to the computer. This allows the computer to know the requesting device address in one read operation.

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Device for Fast I/O Selection

This device is linked to an interruptible computer by a data bus 17, interrupt level lines 18 and input/output (I/O) tag lines 20. When it requests service, it selects itself among all the I/O units connected to the computer. This allows the computer to know the requesting device address in one read operation.

For interruption purposes, I/O unit 1 is connected to interrupt level line I corresponding to its interrupt level priority. It sends a Set interrupt signal (binary value 1) on line 6 when it wants to be selected for an I/O operation.

If no other I/O unit of the same interrupt level and connected to interrupt level I has requested l/O service, line 2 is OFF (binary value 0) and inverter 4 delivers a 1 signal on line 3. AND gate 5 provides a Set signal 1 on line 7 and latch 8 is set. A 1 signal on line 9 is sent to interrupt level line 1 through delay circuit 10.

This signal on line I informs the computer that an I/O unit of interrupt level I requests service. At the same time, it avoids further selection of the other I/O units of the same interrupt level, since these units will receive a 1 signal on line 2 and provide a 0 signal on line 3. AND gate 5 will not deliver a Set signal on line 7. Latch 8 will not be set in the other I/O units.

In the requesting unit, latch 8 is reset by Reset interrupt signal 12 transmitted to the reset input by OR circuit 13 and line 16.

Delay circuit 10, inverter 14 and AND gate 15 avoid the selecti...