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Integrated Circuit Delay Chain With Constant, Self Adjusting Delay Time

IP.com Disclosure Number: IPCOM000083910D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Fuhrmann, H: AUTHOR

Abstract

Delay lines often serve to derive auxiliary click signals from a master clock, e.g., in the control section of computers. In a large-scale integration (LSI) environment, it is desirable to use integrated delay lines, such as chains of logic blocks, each providing a delay according to its switching speed. However, chip-to-chip variations of switching and operating characteristics still necessitate nonintegrated IC delay lines, if accurate delays are required.

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Integrated Circuit Delay Chain With Constant, Self Adjusting Delay Time

Delay lines often serve to derive auxiliary click signals from a master clock, e.g., in the control section of computers. In a large-scale integration (LSI) environment, it is desirable to use integrated delay lines, such as chains of logic blocks, each providing a delay according to its switching speed. However, chip- to-chip variations of switching and operating characteristics still necessitate nonintegrated IC delay lines, if accurate delays are required.

A delay chain of integrated building blocks is proposed, whose length is increased or decreased according to the actual and instantaneous switching speed (delay) of the blocks, as measured on the same chip. As the delay chain and the measuring chain arc situated on the same chip, the variations in the switching behavior of their building blocks are only slight ("tracking effect").

Measuring is effected by applying for an accurately defined period of time, a pulse to a linear chain of switching latches consisting of the same logic elements as the delay line itself. The number of latches switched by the end of the pulse is indicative of the switching speed. The status of the latches is sensed and applied as control information to adjust the length of the delay chain.

The figure shows a specific embodiment using only inverting AND blocks (AI, drawn as empty squares and rectangles), both for the latch chain and the delay chain (DLY). Each latch consists of three Al blocks; output (Cn) and output (Cn') of exclusive OR gate (OE) connected to each latch are fed as control signals to the associated element of chain DLY, consisting of pairs of AI blocks to maintain the polarity of the delayed signal.

The stop and start signa...