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Semiconductor Storage Circuit Utilizing Two Device Memory Cells

IP.com Disclosure Number: IPCOM000083916D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Barsuhn, H: AUTHOR [+3]

Abstract

First and second storage capacitors 10 and 12, shown in Fig. 1, each coupled through a respective transistor 14 and 16 to a pair of bit lines B0 and B1 form a symmetrical memory cell 18, wherein noise signals are eliminated or reduced substantially. Bit lines B0 and B1 are connected to a read amplifier 20 responsive to the difference signal VD produced between bit lines B0 and B1, and to a regeneration circuit 22 which periodically charges bit lines B0 and B1.

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Semiconductor Storage Circuit Utilizing Two Device Memory Cells

First and second storage capacitors 10 and 12, shown in Fig. 1, each coupled through a respective transistor 14 and 16 to a pair of bit lines B0 and B1 form a symmetrical memory cell 18, wherein noise signals are eliminated or reduced substantially. Bit lines B0 and B1 are connected to a read amplifier 20 responsive to the difference signal VD produced between bit lines B0 and B1, and to a regeneration circuit 22 which periodically charges bit lines B0 and B1.

The pulse program indicated in Fig. 2 is used to operate the storage circuit of Fig. 1. During time T1 cell 18 is regenerated by applying a pulse WL to the word line, turning on transistors 14 and if, and a pulse TF to transistor 24 to firmly latch flip-flop circuit 26 of read amplifier 20. Flip-flop circuit 26 includes transistors 28 and 30.

Pulses WL and TF are turned off, and bit lines B0 and B1 are charged to approximately five volts by applying pulse TR during time T2 to transistors 32 and 34. Pulse TR is also applied to transistor 36 to more nearly equalize the voltages on bit lines B0 and B1.

The read period for cell 18 begins during time T3 by first applying pulse WL to the word line, to connect the capacitors 10 and 12 to the respective bit lines B0 and B1 through transistors 14 and 16, to provide a difference voltage between bit lines B0 and B1 which presets latch 26. The polarity of the difference voltage depends upon which of the ca...