Browse Prior Art Database

Dot Matrix Character Generator Using PLA

IP.com Disclosure Number: IPCOM000083920D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Damerell, JB: AUTHOR

Abstract

Dot matrix character generators have been implemented with random AND and OR gate logic, which can be minimized to obtain the lowest device counts. Improved memory technology has since made directly encoding read-only memories (ROM), as exemplified b the EBCDIC character generator in Fig. 1, the most economical embodiment for dot matrix character generators.

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Dot Matrix Character Generator Using PLA

Dot matrix character generators have been implemented with random AND and OR gate logic, which can be minimized to obtain the lowest device counts. Improved memory technology has since made directly encoding read-only memories (ROM), as exemplified b the EBCDIC character generator in Fig. 1, the most economical embodiment for dot matrix character generators.

A slice counter, not shown, is used in addition to the character code input, to sequentially retrieve words having a bit pattern pictorially representing a slice of a character from the same or from sequential planes of the ROM. These words are provided in sequence to a cathode-ray tube (CRT), gas panel display, wire printer or the like, which generates the actual character. A drawback of directly encoding integrated circuit ROM's is that for most character sets, large voids of unused memory space exist.

The programmed logic array (PLA) 5x7 dot matrix implementation example of Fig. 2 shows how an AND array 11 can be used to minimize an OR array 13, by not only eliminating most voids in the integrated circuits, but by further utilizing character slice generating OR elements to generate slices for more than one character, while still allowing direct conversion of character code input to dot matrix slice output. In addition, these same arrays can implement the slice counter and can be easily placed on a single integrated circuit chip.

Each dot in the arrays indicate "don't care" or null connections which are standard features of PLA's, as exemplified by U. S. Patent 3,566,153. Binary 1 and 0 connections within each array are shown as such with the numerals 1 and
0.

The slice count output lines 15, 17, 19 from the toggling flip-flop stages are fed b...