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Shared Macros and Facilities in Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000083934D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Jones, JW: AUTHOR

Abstract

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical AND operations on the input, while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

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Shared Macros and Facilities in Programmable Logic Arrays

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical AND operations on the input, while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

A portion of the read array output operates on feedback registers (JK flip-flop registers). Outputs of these registers are connected as inputs to the associative array.

The design of a system using PLA's is simplified by the use of tried and tested array logic tables; these are array logic macros. Examples of macros are parity checking tables, increment and decrement tables, and shift tables.

The PLA's are restricted in size (number of rows and columns) and in storage function. Thus it is desirable to be able to share macros between several PLA's; also the feedback register should be treated as a shared resource. Applications which do not have a performance problem can be designed with shared macros and shared feedback registers.

Arrays 'A' and 'B' are controlled from a third array which provides common control lines to both arrays (see Figs. 1 and 2).

Rows 1 through 18 of both arrays contain a nine-bit shift macro. This macro transfers the nine bits of JK flip-flop registers one bit position during each cycle of the PLA. The output of the shift registers is achieved by row 19 in both arrays,
i.e., JK flip-flop register position 9 is transferred to the output position (A OUT or B OUT). The shift registers are connected in series by connecting A OUT to the input of the shift register of array B, and B OUT to the input of the shift register of array A.

A control field of 1011 selects the shift macro in both PLA's, and enables their contents to be rotated. A control field of 1001 selects the shift macro in array A only, while 1010 selects the shif...