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Asynchronous Sequential Control Using Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000083935D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Jones, JW: AUTHOR

Abstract

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical ATM operations on the input while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

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Asynchronous Sequential Control Using Programmable Logic Arrays

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical ATM operations on the input while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

A portion of the read array output operates on feedback registers (JK flip-flop registers). Outputs of these registers are connected as inputs to the associative array.

The design of a system using PLA's is simplified by the use of tried and tested array logic tables; these are array logic macros. Examples of macros are parity checking tables, increment and decrement tables, and shift tables.

A network of PLA's (PLA A - Fig. 1 in two parts; PLA B - Fig. 2) is organized to control the operation of a dynamic shift register. This shift register is similar to a delay line in that it cyclically shifts data from one stage to the next. Eight such channels are connected in parallel as an 8 wide shift register for maintaining six character bits and parity, while the eighth channel is used for a tag. The outputs and inputs of these channels are connected together via rows 1-8 of PLA A.

The data transfer between shift stages is clocked at the same rate as the PLA's. The start and end of a variable-length record are identified by a special character and a tag bit, respectively. A read operation requires sequential operations in PLA A.

The first operation uses row 49 to condition JK12A, JK10A as controls, whereby a path is made for the data on input pin positions 1 through 8 to be gated to the JK flip-flop registers positions 1 through 8 via rows 9 through 24. This path is subsequently opened when the tag bit is detected on input 8 by selecting row 50. The character required to be read is identified by the tag bit. The contents of the JK flip-flop registers are presented on output positions 10 through 16, while the read command is still active, via rows 32 through 39.

The read operation requires a sequence of such macro commands to be executed within PLA A. The first is as described above. The second is the parity checking of the data read from the buffer. A third macro instruction advances the tag bit one stage position relative to the data. This advancing of the tag enables the system to read the next character dur...