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Transmission Line Adapter Implementation Using Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000083936D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 160K

Publishing Venue

IBM

Related People

Jones, JW: AUTHOR

Abstract

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical AND operations on the input, while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

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Transmission Line Adapter Implementation Using Programmable Logic Arrays

A programmable logic array (PLA) is a structure consisting of an associative array coupled to a read array. The associative array performs logical AND operations on the input, while the read array combines the contents of the selected words such that outputs are the result of ORing selected words.

A portion of the read array output operates on feedback registers (JK flip-flop registers). Outputs of these registers are connected as inputs to the associative array.

The design of a system using PLA's is simplified by the use of tried and tested array logic tables; these are array logic macros. Examples of macros are parity checking tables, increment and decrement tables, and shift tables.

A network of interconnected programmable logic array (PLA) structures provides adapter (data handling and control) functions, for interfacing with a bit- serial type transmission line facility.

Logic arrays A, B and C (Figs. 1-3) operating synchronously from a common clock source, are structured to enable PLA A to form the serializing and deserializing functions at the transmission interface. PLA B provides sequence control, while PLA C subdivides an oscillator input to provide timing pulses for controlling the line interface.

Fig. 1 shows PLA A programmed so that rows 1 through 18 form a shift register operation for serializing and deserializing functions on the line. The input from the line is connected to input 7 of the PLA, while the output to the line is connected to position 1 (JK9A) of the output register. Data for transmission is received in parallel on inputs (columns) 8 through 14 of PLA A, and translated through rows 27-33 into the JK flip-flop register (JK1A-JK8A) under the control of inputs 15 through 18. The control field is generated in PLA C and will be described later. Deserialized data is gated to output positions 2 through 8 of PLA A via rows 20 through 26.

Special control characters and terminal addresses are detected in rows 41 through 49 and generated for transmission in rows 50 through 53. Generation of control characters is controlled by the decode of the control field from PLA C.

The control characters detected in PLA A are encoded on outputs 13 14, 15 and 16, which are connected to inputs 12, 14, 16 and 18 of PLA B (Fig. 2).

PLA B receives the sequence of encoded control characters and address matching information for updating the state of the adapter. A sequence of commands to the addressed adapter determines its operation. One sequence sets up a receive state in the adapter whereby the adapter receives data for printing, while another sequence in...