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Function Oriented Homing Sequence Generator

IP.com Disclosure Number: IPCOM000083945D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 5 page(s) / 68K

Publishing Venue

IBM

Related People

Brown, A: AUTHOR [+4]

Abstract

INTRODUCTION: The criteria of fault detection in a sequential circuit is to derive an input test sequence, which distinguishes the response (output sequence) of the good or fault-free machine from that of the faulty machine. In the process of generating test sequences, known as a checking experiment, it is generally necessary that the machine under test be put into a known initial state. An input sequence that accomplishes this is referred to as a homing sequence.

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Function Oriented Homing Sequence Generator

INTRODUCTION: The criteria of fault detection in a sequential circuit is to derive an input test sequence, which distinguishes the response (output sequence) of the good or fault-free machine from that of the faulty machine. In the process of generating test sequences, known as a checking experiment, it is generally necessary that the machine under test be put into a known initial state. An input sequence that accomplishes this is referred to as a homing sequence.

The method outlined herein generates a homing sequence for a logical sequential circuit which is represented by its Logic Flow Graph (LFG) model. The LFG is a directed graph which may be labeled so that it can serve as an efficient data base for the homing sequence generator. FOSGEN includes a process in which the task of homing-sequence generation is broken into several separate subtasks, thereby reducing the amount and complexity of processing at each step. For example, forward path and latch-up conditions are handled separately, thereby reducing the search space for forward path building and for establishing latch-up conditions.

FOSGEN is definitive for "simple iterative circuits". For such circuits, either no homing sequences exist, or, at least one homing sequence exists, in which all function variables switch states at most once.

THE LFG MODEL. For computational processing, the logic flow graph can be represented in one of several formats. The algorithms here are based on the AND-OR macro representation. In using this representation, three types of blocks are associated with each macro.

First, an OR block, which is the state of the node represented by the macro. Second, an AND block whose inputs do not include the OR block in the macro. (This AND is classified as an AF block, meaning an AND condition in a forward path.) Third, an AND block whose inputs always include the OR block in the macro. (This AND is classified as an AL block, meaning an AND condition for latchup.) Since AL implies a self-loop in the macro, no connection from the OR output to the AND is necessary. The AND/OR macro representation of nodal state e(z) (Fig. 1) is shown in Fig. 2.

FOSGEN OVERALL INTERFACE DIAGRAM. At the system level, the homing-sequence generation interfaces are shown in Fig. 3. Initially a transformation step takes the primitive (ALD) level input description and generates the logic flow graph at the output. The homing-sequence generator is then called to generate a specified "home" state for the logic via the control card. The output of the homing-sequence generator can be either hard copy or a data set, which interfaces with other parts of a test generation system.

The homing-sequence generator itself can be broken down into three parts (Fig. 4).

Part 1 is a program that inputs the logic flow graph and generates a Flow Graph Ordering Map (FORMAP). The map generation incorporates a weighting scheme which utilizes the functional proper...