Browse Prior Art Database

Programmable Control Store Clock

IP.com Disclosure Number: IPCOM000083946D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Jones, DS: AUTHOR [+2]

Abstract

This programmable clock uses a memory (or array) to develop the desired output timings. It is fully programmable through a computing system. The memory word size and bit size determine the capacity of the clock (i.e., cycle-time capacity and number of output timings), and is specified by the user. The number of words (addresses) determines the maximum cycle-time capability of the clock (maximum cycle time of the clock equals the cycle time of the array times the number of words). The number of bits determines the maximum number of output timings (maximum number of outputs equals the number of bits divided by two). A pair of bits are used per output timing.

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Programmable Control Store Clock

This programmable clock uses a memory (or array) to develop the desired output timings. It is fully programmable through a computing system. The memory word size and bit size determine the capacity of the clock (i.e., cycle- time capacity and number of output timings), and is specified by the user. The number of words (addresses) determines the maximum cycle-time capability of the clock (maximum cycle time of the clock equals the cycle time of the array times the number of words). The number of bits determines the maximum number of output timings (maximum number of outputs equals the number of bits divided by two). A pair of bits are used per output timing.

The memory can be implemented in two ways: 1) a straight array arrangement, or 2) an interleaved arrangement. In the straight array arrangement only one array is utilized, where in the interleaved arrangement more than one array is utilized, each array being addressed an increment of delay after the preceding one. For example, assume the arrays have a cycle time of 100 nanoseconds, array number 1 is addressed at time T(0), then array number 2 at T(0)+25 nanoseconds, array number 3 at T(0) + 50 nanoseconds, array number 4 at T(0)+75 nanoseconds, then back to array number 1 for the next address.

Data out bits for each array can then occur in 25 nanosecond increments. The bit outputs from the arrays are hardware OK'ed together (i.e., all bit 00's, all bit 01's, etc.). At each address selected, each of the bits in the array will appear as data out at the access time of the array. Interleaving gives the appearance of an array cycling faster than...