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Test Method and Apparatus for Dynamic Shift Register

IP.com Disclosure Number: IPCOM000083954D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Ferris, G: AUTHOR [+4]

Abstract

A field-effect transistor (FET) serial shift register stores data in the form of a charge on a capacitor and this charge, or the absence of a charge, is shifted from one storage cell to the next in the normal operation of the shift register. The shift operation also restores the level of charge on the storage capacitors, and it is useful to test a shift register for its ability to hold data during a pause while the normal shift operation is interrupted. The apparatus of Fig. 1 provides a sequence of data patterns for this test, and Fig. 2 shows a sequence of data patterns.

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Test Method and Apparatus for Dynamic Shift Register

A field-effect transistor (FET) serial shift register stores data in the form of a charge on a capacitor and this charge, or the absence of a charge, is shifted from one storage cell to the next in the normal operation of the shift register. The shift operation also restores the level of charge on the storage capacitors, and it is useful to test a shift register for its ability to hold data during a pause while the normal shift operation is interrupted. The apparatus of Fig. 1 provides a sequence of data patterns for this test, and Fig. 2 shows a sequence of data patterns.

A 5-bit shift register illustrates the test on a register of conventional size. A clock provides a signal to shift the register and a trigger circuit provides a signal to the shift register to store either a 1 or a 0 at its input stage, according to the state of the trigger circuit.

A data counter counts the clock pulses and a count decoder circuit triggers the trigger circuit when this count equals 5, the number of stages in the register. Thus these components cooperate to load the shift register serially with alternate sequences of five 1 bits and five 0 bits. This data pattern is shown in the line Data In in Fig. 2. Dashes in Fig. 2 represent pauses when the clock is stopped and no new data is entered into the register.

A shift counter also counts the clock pulses and a count decoder circuit produces an output pulse when the count alternat...