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Browse Prior Art Database

Counter With Fast Reset

IP.com Disclosure Number: IPCOM000083955D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Green, JK: AUTHOR [+2]

Abstract

Latches 2 and 3 are two stages of a binary counter having a number of stages. When a clock pulse 7 is applied to the counter, the leftmost stage, not shown, is triggered from its existing binary state to the opposite state. When the output of the leftmost stage switches from a 0 to a 1, a carry occurs in the counting process that triggers the next stage and each subsequent stage to and including the leftmost stage that holds a 1. The 1 to 0 transition that this stage undergoes does not produce a further carry.

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Counter With Fast Reset

Latches 2 and 3 are two stages of a binary counter having a number of stages. When a clock pulse 7 is applied to the counter, the leftmost stage, not shown, is triggered from its existing binary state to the opposite state. When the output of the leftmost stage switches from a 0 to a 1, a carry occurs in the counting process that triggers the next stage and each subsequent stage to and including the leftmost stage that holds a 1. The 1 to 0 transition that this stage undergoes does not produce a further carry.

In the counter of the drawing, an AND gate 4 receives a carry signal from the 1 output of the latch 2 and the latches, not shown, of each preceding state. Where each preceding stage is a 1, AND gate 4 and associated inverter 5 respond to the next clock pulse to trigger latch 3.

The number of stages for which carry signals can be grouped in this way depends on the number of inputs that can be accepted by AND gate 4. AND gate 4 permits more stages to be grouped than if the carry signals were applied directly to the latch. However, gates 4 and 5 introduce an undesirable delay in the circuit during reset. A reset signal is applied to line a to reset the counter to all 0 values. During a reset operation, the latches previously holding a 1 are reset to 0 and the output of gate 4 is switched from a 0 to a 1, and the output of gate 5 is switched from a 1 to a 0.

The earliest time that the counter can be restarted after a reset operation is w...