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Generating Unique Names for Virtual Segments

IP.com Disclosure Number: IPCOM000083958D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+4]

Abstract

Each segment name may consist of two 24-bit fields, X and Y.. The X field is incremented as a binary counter when Y has gone through 2 states. The Y value may be generated by the circuit shown in the figure. The register called Y' is a binary counter with bit 23 being the low-order (fastest changing) bit. The register Y receives the derived Y value according to the following hashing rules, in which signifies the exclusive OR function: 1) Bits Y (0 - 5) = Y' (0 - 5) 2) Bit Y (6) = Y' (6) + Y' (18) Y (7) = Y' (7) + Y' (19) Y (8) = Y' (8) + Y' (20) Y (9) = Y' (9) + Y' (21) Y (10) = Y' (10)+ Y' (22) Y (21) = Y' (11)+ Y' (23) 3) Bits Y (12 - 23) = Y' (12 - 23).

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Generating Unique Names for Virtual Segments

Each segment name may consist of two 24-bit fields, X and
Y.. The X field is incremented as a binary counter when Y has gone through 2 states. The Y value may be generated by the circuit shown in the figure. The register called Y' is a binary counter with bit 23 being the low-order (fastest changing) bit. The register Y receives the derived Y value according to the following hashing rules, in which signifies the exclusive OR function: 1) Bits Y (0 - 5) = Y' (0 - 5)

2) Bit Y (6) = Y' (6) + Y' (18)

Y (7) = Y' (7) + Y' (19)

Y (8) = Y' (8) + Y' (20)

Y (9) = Y' (9) + Y' (21)

Y (10) = Y' (10)+ Y' (22)

Y (21) = Y' (11)+ Y' (23)

3) Bits Y (12 - 23) = Y' (12 - 23).

Exclusive OR circuit 101 in the figure executes rule 2.

Each new segment name generation begins by incrementing the Y' counter by 1, before performing the hashing and transfer operation defined by rules 1), 2) and 3).

Bits 18 to 23 of register Y may then be used to address a section of a hash table. The hash table section may be located in different modules in the real memory of the computer system.

Bits 6 through 17 of register Y are hashed in exclusive OR circuit 102 with bits 9 to 20 of a provided byte address in the named segment, to generate an offset into the addressed hash table section to select an entry, which may directly or indirectly provide the address in real memory of the byte in the segment.

This system gives good entry dispersion in the hash table an...