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Shared Interrupt/Cycle Steal Priority

IP.com Disclosure Number: IPCOM000083968D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+2]

Abstract

Control logic for interrupt, cycle steal, machine check and the main processing level is shared. A common priority logic tree is shared by the interrupt polarity holds and the cycle steal latches, with cycle steals having priority over interrupts. Outputs from the common logic tree are encoded into a group of signals for selecting local storage resistors (LSR's), which are to be used for servicing the interrupt or cycle steal.

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Shared Interrupt/Cycle Steal Priority

Control logic for interrupt, cycle steal, machine check and the main processing level is shared. A common priority logic tree is shared by the interrupt polarity holds and the cycle steal latches, with cycle steals having priority over interrupts. Outputs from the common logic tree are encoded into a group of signals for selecting local storage resistors (LSR's), which are to be used for servicing the interrupt or cycle steal.

The overall arrangement is shown in Fig. 1, where interrupt levels 1-5 priority logic and cycle steal priority logic are represented by blocks 10 and 20, respectively. These blocks feed common priority encode logic 40. Blocks 10, 20 and 40 are external to the central processing unit (CPU) and by use of the common priority encode logic, the number of Lines entering the CPU for this function is reduced to three.

The highest priority processing level is Machine Check, block 60, which is internal of the CPU. Cycle steals, as a class, are at the next level of priority and they are followed by a class of interrupts. The main program level has the lowest priority and is a default level. Flip-flops 66, 67 and 68 are set by signals from logic 40 under control of a CLOCK LSR SELECT PRIORITY timing signal. Flip- flop 69 is set by a signal from Machine Check logic 60, and although flip-flop 69 and any one of the flip-flops 66, 67 and 68 could be set simultaneously, the output of flip-flop 69 inhibits the outputs of flip-flops 66, 67 and 68 from I reaching LSR SELECT logic 80. This is accomplished by feeding the minus level output of flip-flop 69 into AND circuits 71, 72 and 73.

The cycle steal priority logic 20 is shown in detail in Fig. 2 There are three levels of cycle steal and the level for servicing high-speed I/O devices, i.e., disk storage drives (Fixed Disk Burst Mode Cycle Steal) has the highest priority. The next level of priority is for lower speed I/O devices and in this instance is called an Expansion Cycle Steal level. The lowest priority cycle steal level shown is the Base Cycle Steal Level.

Cycle steal requests occur asynchronously relative to each other and a lower level cycle steal that is in progress can momentarily block a higher level cycle steal, until the current cycle is completed. The Fixed Disk Cycle Steal is requested by a -FD BPC signal. This signal is inverted by inverter 22 and the inverted signal is passed by AND circuit 23, it expanded cycle steal trigger 24 and base cycle steal latch 21 are not set at T7 time.

The -FD BPC signal normally inhibits the settin...