Browse Prior Art Database

System for Averaging 0's and 1's in a Memory

IP.com Disclosure Number: IPCOM000083990D
Original Publication Date: 1975-Aug-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Dennard, RH: AUTHOR [+2]

Abstract

Described is a scheme for reducing the probability of occurrence of many successive "1's" or "0's" in metal-nitride-oxide semiconductor (MNOS) structures.

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System for Averaging 0's and 1's in a Memory

Described is a scheme for reducing the probability of occurrence of many successive "1's" or "0's" in metal-nitride-oxide semiconductor (MNOS) structures.

If pulsed alternately at less than saturation, MNOS structures settle down to some steady-state value of high and low thresholds. However, in a real memory environment, it is probable that many more 0's than 1's will be written even on a random basis. In some cases, a long string of 0's or 1's could be written.

If the device were not saturated, the repeated 0's would drive the threshold so far negative, that when a 1 pulse finally arrived, it might not switch into the 1 state. To avoid this problem, and to generally tighten tolerances of the threshold window, it is desirable to insure that no long string of 1's or 0's occurs.

To achieve this, an inverter is placed in the writing circuit. The inverter is switched into the circuit on a random basis for each word written. The first bit or bits would indicate whether it had been inverted or not. On readout, another inverter would or would not be switched, depending on the first bits. Thus, a truly random probability of 0's or 1's could be achieved at very little loss in access or writing times.

Only a single write pulse would be needed to put the information on a bit, in contrast to some elaborate balanced write pulse schemes. This approach should apply to and nonsaturating memory element.

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