Browse Prior Art Database

Regaining Synchronization on a Serial Bubble Domain Chip

IP.com Disclosure Number: IPCOM000084019D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Barrett, GG: AUTHOR

Abstract

A dedicated on-chip loop of a magnetic bubble domain chip is interfaced with a volatile dynamic shift register for regaining synchronization following a power failure.

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Regaining Synchronization on a Serial Bubble Domain Chip

A dedicated on-chip loop of a magnetic bubble domain chip is interfaced with a volatile dynamic shift register for regaining synchronization following a power failure.

Tape loops for storing information serially by byte generally have an opening, or other suitable means, for indicating the beginning of memory. With a serially organized bubble memory shift register, feasible means of indicating the beginning of memory are absent. Dedicated on-chip loops for clocking and counting, taken alone, only provide relative information.

In order to provide for more than one reference point, keep ancillary structure to a minimum, and provide simple interfacing, the dedicated on-chip loop is controlled by an off-chip volatile dynamic shift register. The off-chip register is to contain the same information as the on-chip loop. Feedback connections exist only on the off-chip register, and control both.

Information in the off-chip register will be lost upon a power failure. Sufficient system energy will exist to stop the chip at a predetermined phase and to insure retention of proper on-chip status.

When power is again turned "on", a status character is shifted a predetermined number of shifts (N) off of the chip and into the off-chip register without applying the feedback connections. Then the feedback connections are applied, and the off-chip register is shifted N shifts. The synchronization information is now contained...