Browse Prior Art Database

Making a One Device Memory Cell

IP.com Disclosure Number: IPCOM000084039D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR [+2]

Abstract

Leakage control in a memory cell of the type disclosed in U. S. patent 3,841,926 is provided by placing a field shield over recessed oxide. The method also lends itself to providing reduced bit line capacitance.

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Making a One Device Memory Cell

Leakage control in a memory cell of the type disclosed in U. S. patent 3,841,926 is provided by placing a field shield over recessed oxide. The method also lends itself to providing reduced bit line capacitance.

An array of these memory cells, each of which includes a field-effect transistor and a storage capacitor, is made by first forming a 50 angstrom layer of silicon dioxide over a silicon surface followed by a first 250 angstrom layer of silicon nitride. A recessed oxide patter is formed in the silicon surrounding the drain, gate and source regions of the transistor, by etching through the silicon nitride and silicon dioxide into the surface of the silicon. Silicon dioxide is then thermally grown in the etched region of the silicon, up to the original surface of the silicon to produce the recessed oxide.

The remainder of the first layer of silicon nitride is removed and a second layer of silicon nitride, 250 angstroms thick, is deposited, and source and drain regions are etched therein. A 5,000 angstrom layer of doped silicon dioxide is now deposited, and the dopant therein is driven into the silicon through the source and drain openings in the silicon nitride. The doped silicon dioxide layer, the second silicon nitride layer and the 50 angstrom layer of silicon dioxide is removed from the surface of the silicon.

With the recessed oxide and the source and drain regions formed in the silicon, as indicated in Figs. 1, 2 and 3, a thin 250 angstrom layer of silicon dioxide is grown on the silicon followed by a third 250 angstrom layer of silicon nitride, a 3000 angstrom layer of polysilicon and a fourth 250 angstrom layer of silicon nitride. The fourth layer of silicon nitride is etched to define openings over the drain regions, which are also used as bit lines for the cells. The expos...