Browse Prior Art Database

End of a Bit Line Sensing System

IP.com Disclosure Number: IPCOM000084043D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Rossi, FR: AUTHOR

Abstract

The system provides rapid sensing at the end of a bit line of a memory array of, e.g., one-device cells, which requires small bit line voltage swings when reading 0 and 1 bits of information from the array.

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End of a Bit Line Sensing System

The system provides rapid sensing at the end of a bit line of a memory array of, e.g., one-device cells, which requires small bit line voltage swings when reading 0 and 1 bits of information from the array.

The sense latch is arranged such that a low impedance is provided between node A and ground when a 1 is being read from a one-device cell, e.g., having transistor T1 and capacitor CS which is controlled by word line W/L, and a high impedance is provided when a 0 is being read. With the binary information to be read out in the sense latch, a pulse R is applied to transistor T2 to precharge node A to, e.g., 4.5 volts and to transistor T3 to precharge node B to, e.g., 6.5 volts. A bias or reference voltage Vref. of, say, 4 volts is applied to a read latch.

Assume that a 1 is to be read out. A set pulse is applied to the sense latch and transistor TBS, which connects node B or the data line to node A or the bit line, is turned on by a pulse at VBS. Since the sense latch acts as a low impedance, current flows through the sense latch rapidly discharging both nodes A and B. Within approximately 75 nanoseconds node B is discharged to a voltage less than 3.5 volts and a read pulse turns on the read latch, which is flipped in a first condition indicative of a 1 bit of information.

The output from the read latch controls a data output circuit having transistors T4 and T5, the read latch output being connected to the gate of T5 while a del...