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Preconditioning Latch

IP.com Disclosure Number: IPCOM000084052D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Reinhart, GR: AUTHOR

Abstract

Described is a preconditioning latching circuit that will provide either similar or dissimilar polarities to test circuits that have indeterminate outputs, by feeding the output of the device under test back to the latching circuit.

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Preconditioning Latch

Described is a preconditioning latching circuit that will provide either similar or dissimilar polarities to test circuits that have indeterminate outputs, by feeding the output of the device under test back to the latching circuit.

As shown in the figure, the preconditioning latching circuit comprises an input 9, which is fed through a differential amplifier 10 and parallel delay circuits 11 and 12 to parallel differential amplifiers 13 and 14. Each of these differential amplifiers, in turn, feeds four parallel logic circuits 15, 16, 17, and 18. These logic circuits 15 to 18 are coupled to a driver circuit 19 having a differential output on lines 26 and 27, and to the latch 20 to provide a specific input to a device 21 under test (DUT).

The outputs of the logic circuits 16 and 17 provide a set signal to the latch 20, while the outputs of the logic circuits 15 and 18 provide a reset signal to the latch
20. The output 25 of the device 21 under test is fed back, via lines 23 and 24, to logic circuits 15 and 18 to reset the latching circuit 20, to cause the latching circuit 20 to change its output if the output of the device 21 under test was not the desired result.

A device under test that has an indeterminate output could produce the following results:
Line 26 or 27 Output 25
Voltage "HI" HI or Lo immediately followed by voltage "Lo". Opposite polarity of the previous state.

The unique feature of the described preconditioning latch (PCL) is that it is a programmable circuit that will provide similar or opposite polarities, which ever is required, to a device 21 under test that has an indeterminate output. The preconditioning latch is able to align the output of the DUT 21 into a known state by use of a predetermined input logic sequence. B. Usage. (a) Circuits having an output that responds only to negative input transitions. Logic Sequence for Preconditioning DUT Output When the activating signal is on line 27: Input 9 Output 25 1 Indeterminate 0 1 1 0 0 1.

(b) Circuits having an output that responds only to positive input transitions. Logic Sequence for Preconditioning DUT Output When the activating signal is on line 2...