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Fault Isolations in Shift Register Latches

IP.com Disclosure Number: IPCOM000084066D
Original Publication Date: 1975-Sep-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Chao, CC: AUTHOR [+3]

Abstract

I. OBJECT. Presently LSI (large-scale integration) logic chip technology can call for a large portion of the circuitry to be devoted to shift register latches (SRL's). At the present time, in regular chip test, only limited functional test ("flush test") is provided for the testing of the SRL's. If a chip fails to pass this test, it will show that the SRL's probably do not function properly, but no diagnostic data is provided to pinpoint which SRL (or SRL's) of the SRL chain failed, how they failed (which input or output failed, etc.), etc. This technique answers a need to provide a unique tool for SRL diagnostics.

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Fault Isolations in Shift Register Latches

I. OBJECT

Presently LSI (large-scale integration) logic chip technology can call for a large portion of the circuitry to be devoted to shift register latches (SRL's). At the present time, in regular chip test, only limited functional test ("flush test") is provided for the testing of the SRL's. If a chip fails to pass this test, it will show that the SRL's probably do not function properly, but no diagnostic data is provided to pinpoint which SRL (or SRL's) of the SRL chain failed, how they failed (which input or output failed, etc.), etc. This technique answers a need to provide a unique tool for SRL diagnostics.

II. PROCEDURE FOR FAULT ISOLATION IN SHIFT REGISTER LATCHES (SRL)
1. Identify all SRL's in a logic chip, and each SRL's input/output signal lines, as well as their functions and related connections.
2. Select one out of a number of combinations of potential SRL input and/or output stuck faults. Once the predetermined selection is made, a list of such faults will be formed automatically.
3. Using a conventional sequential test pattern generator, test patterns are created to detect the stuck faults from the fault list formed in Step 2.
4. From simulation of the selected faults, generate a "fault dictionary" which contains the detectable SRL fault(s) with the corresponding test pattern and number, and related measurable chip output.
5. Merge the logic model with the physical layout design data, to pinpoint physical cell location in X-Y coordinates on the chip versus each selected SRL stuck fault for diagnostic observation or operations, etc.

III. BRIEF ALGORITHM DESCRIPTIONS.

The physical design data of the chip to be tested is used as the main source of data. The SRL's, in terms of macros, are identified, based on block rules, and circuit types. Analyzing the SRL macros enables the macro structure b...